This invention relates to a method and system for displaying visual information on a screen by line by line and point by point sweeping.
Some methods and systems of this type are described in the following patents and patent applications:
FR No. 2 406 250, EP No. 0 055 167, EP No. 0 056 207, EP No. 0 055 168, EP No. 0 054 490, and U.S. applications Ser. No. 583,072 filed Feb. 23, 1984 and assigned to Texas Instruments Incorporated, U.S. Pat. No. 4,623,986 issued Nov. 11, 1986 and assigned to Texas Instruments Incorporated, and U.S. Pat. No. 4,620,289 issued Oct. 28, 1986 and assigned to Teas Instruments Incorporated.
These prior systems teach a method for displaying visual information on a screen by line by line and point by point frame sweeping, including:
(a) Controlling all the operations of image display and composition by means of related address and data fields provided by a programmed central processing unit, this central processing unit cooperating with a memory and a video processor by a multiplexed time sharing data and address bus for preparing each frame and displaying it on said screen.
(b) Controlling access to said memory as a function of predetermined priorities with a dynamic access circuit for the memory.
(c) Assigning to certain addresses in said address fields an instruction function for the video processor so that it can utilize the consecutive data field at this address for its own needs.
(d) Distributing the consecutive data fields, as a function of the address field assignment, either to the memory or to said video processor.
In the method described in the above cited patent application No. 83 03 142, a data field, following an address field interpreted as an instruction for the video processor can be reused as many times as necessary without the intervention of the central processing unit, the video processor operating on a series of consecutive addresses from the initially provided address, calculating them in its own calculation unit. Such a repetitive operation can be useful, for example, in preparing in the memory a page to be displayed in which a large portion is made up of a single background color. In these conditions, the data representing this color can be loaded into the adjacent emplacements of the memory by increasing each time the address by a unit, all of this being controlled by the memory dynamic access control circuit.
This procedure entails the considerable advantage of discharging the central processing unit from a part of its task and thereby gaining a considerable amount of processing time. A central processing unit consisting of a microprocessor has a cycle time in the order of one microsecond, while the access time to the memory, if it is effected by the video processor, is about one hundred nanoseconds.
It would therefore be desireable to release the central processing unit of all of its "secondary" tasks, which are not directly connected with the control of the system, as, for example, the animation of a part of the image, changing a form, rotating a part of an image, etc.